The present invention relates to a digital signal processor, and more particularly, to a digital operation unit using multiple registers.
In general, a digital operation unit includes an arithmetic logic unit and a register. FIG. 1 is a block diagram illustrating the structure of a conventional digital operation unit consisting of an arithmetic logic unit (ALU) 10 operable to execute various arithmetic and logical operations, a register 20 storing data output from ALU 10, a bus 30 for transmitting data, switches 40a and 40b controlling data transmission on bus 30, and switches 50a and 50b controlling transmission of data output from register 20.
Data output from ALU 10 of the conventional digital operation unit is stored in only register 20. Accordingly, an external memory (not shown) connected to bus 30 is required to perform operations on data output from ALU 10. That is to say, in order to execute a variety of complex arithmetic and logical operations, frequent data shifts to and from an external memory are necessary because of the single data register 20. This requirement lowers the overall operating speed of the digital signal processor.